In a conventional semiconductor integrated circuit having a multiport register file, a plurality of functional blocks are connected to the multiport register file so that the functional blocks can process data in parallel.
For example, Patent Document 1 uses a register file of a multiport type where the number of write ports is 2 and the number of read ports is also 2 (2-Write 2-Read (2W2R)-type), wherein a 1W1R-type functional block and another 1W1R-type functional block are connected to the 2W2R port-type register file. Specifically, the 2W2R port-type register file provides two read ports and two write ports for one memory cell, wherein one read port and one write port are connected to a first functional block while the other read port and the other write port are connected to a second functional block.
It has been disclosed in Non-Patent Document 1, for example, that for such a transistor circuit including memory cells, there is a relationship between the threshold voltage of constituent transistors, the supply voltage to the constituent transistors, the activity rate of the constituent transistors and the power consumption thereof, i.e., there exist a threshold voltage and a supply voltage that minimize the power consumption under any given activity rate.
Patent Document 1: Japanese Laid-Open Patent Publication No. 11-175394 (FIG. 13)
Non-Patent Document 1: K. Nose et al., Optimization of VDD and VTH for low-power and high-speed applications, ASPDAC.00, pp. 469-474, January 2000.